(GB2246252-B)      A rechargeable battery management module comprising a control unit PCB assembly, either mounted on a box housing 6 Nicad AA cells to equal the overall size of a PP9 dry battery or separately installed with 4 to 8 individual AA, C or D Nicad cells, enabling the replacement of either type of dry battery in-situ in portable equipment, wherein the control unit supervises the Nicad battery recharge and discharge cycling, the means for recharging being adapted from a known automatic timing circuit whereby an astable clock IC produces count pulses for a CMOS multi-stage binary counter IC controlling a PNP transistor driving a LED-regulated Darlington constant-current output stage feeding the Nicad battery negative pole, with its positive pole being routed via a blocking diode, forward-biased in recharge, to the VS+ rail of a VS+- dc supply provided from either the equipment's mains PSU or an external source, but since the counter output stage had returned to logic high to turn-off the PNP driver and terminate the previous recharge, a momentary positive-going pulse is now required to again reset all the counter binary stages to logic low to turn-on the PNP driver, restart the clock and commence the next recharge; the said reset pulse is derived from the known reset capacitor connected across the unit's VS+- supply input with the capacitor upper plate at VS+ rail and its lower plate linked to the counter's reset pin and also via a timing resistor to the VS- rail; when the user connects the VS+- power lead the capacitor lower plate rises momentarily with the upper plate to the VS+ rail to generate the required positive-going counter reset pulse to initiate a timed continuous fast recharge; but since the known reset circuit offers little overcharge protection against a temporary loss of recharge power causing unwanted counter resets, and since said resets can occur at both disconnection and reconnection of the VS+- supply, means provided whereby the known reset circuit is adapted to include two extra diodes and a resistor to inhibit either cause of counter IC reset once recharge has commenced; the first diode being normally reverse-biased by its cathode link to the reset capacitor lower plate and its anode to VS-, becomes forward-biased to suppress and to thereby inhibit a momentary negative-going capacitor pulse seen to recharge power disconnection to cause a reset during its discharge; the added resistor being connected between the lower plate of the reset capacitor and the reset pin of the counter IC, the second diode having its anode connected to said reset pin and its cathode connected to the counter output, whereby the second diode is initially reverse-biased by its cathode link to the counter output, logic high prior to recharge; this enables the initial positive-going pulse to reset all the counter binary stages to logic low to start the recharge but this second diode now becomes forward-biased to suppress and thereby inhibit any further counter resets related to positive-going pulses produced by VS+- reconnection after temporary breaks; by this means the user can safely suspend recharge for one or more convenient breaks, e.g. overnight, with its progress memorized by sourcing the counter IC's VCC+- supply continuously from the Nicad battery to maintain the logic state of all the counter binary stages during the said breaks; after each break the clock pulses resume until reaching the total count required to terminate the delayed recharge; means provided to ensure the PNP driver is fully turned-off when the counter IC output rises to logic high to terminate a recharge    whereby the emitter of the PNP driver is connected via a forward-biased diode to VS+ to offset the blocking diode voltage drop between VS+ and the counter IC's VDD+ pin fed from the Nicad battery B+ pole; means to offset VS+ load changes and to stabilise Nicad constant-current during recharge, said means including a resistor connected in series between the collector of the said PNP driver and the cathode of a 2.7V zener diode which is connected at its anode to the VS- rail, and a dropper resistor connected at one end to the cathode of the zener diode and at its other end to the base of the Darlington stage, with the LED being connected between the VS- rail and said other end of the dropper resistor; means provided whereby two Schottky diodes and two resistors form a current-divider circuit enabling moderate equipment current during recharge effectively isolated from the Nicad constant-current supply whereby one forward-biased diode with its cathode at VS- feeds equipment current via a limiting resistor to the B-1 output terminal; the second diode is initially reverse-biased by its cathode at the Nicad B- pole and anode at B-1 terminal, with the Nicad B- pole standing voltage raised to about 2.4 Vdc w.r.t. VS- during recharge by a resistor connected in series between the Nicad B- pole and the collectors of the Darlington stage; when recharge ends, the VS+- supply continues to feed the equipment and the Nicad battery is blocked until the external power lead is removed, whereupon the two current-divider diodes reverse state to enable the Nicad battery to power the equipment via the module B+2, B-1 output terminals; means provided for generating warning bleeps to remind the user to remove the external power lead when recharge has terminated with the equipment switched OFF, dependent on the equipment ON/OFF switch being located in its negative supply rail, and when ON provided on earth return via the module OV terminal to power the Nicad discharge monitoring circuit; this enables a zener diode, shunted by a high value resistor, and fitted between the module OV and VS- rails, to conduct when the VS+- supply voltage rises above its normal level when off-load and thereby energize the monitor CMOS quad 2-input NAND gate bleep generator IC; and automatic means for monitoring the gradual decrease in Nicad battery voltage during equipment operation from about 1.4 V per cell after a recharge to the 1.0 V end-point level includes a known NPN emitter-follower and its associated NPN driver transistor circuit; the NPN emitter-follower operates at constant-current to provide a constant collector-emitter voltage drop, presettable by means for adjusting its base voltage, enabling the decrease in Nicad B+ voltage at its collector to be transferred to its emitter load resistor whereby the initially high voltage turns the NPN driver hard-on and the very low NPN driver collector voltage is adapted to drive a PNP output limiter in the B+2 output rail into full conduction, and also to inhibit the CMOS quad 2-input NAND gate bleep generator IC; monitoring continues with the Nicad battery and NPN emitter-follower voltages slowly falling in step for many operating hours until the Nicad voltage nears 1.0 V per cell, the end-point level to which the NPN emitter-follower base preset has been adjusted to ensure its falling emitter output starts to turn-off the NPN driver and the rising collector voltage of the said NPN driver activates the CMOS quad 2-input NAND gate, IC thereby generating bleeps from its associated piezo buzzer and also progressively reduces the PNP limiter output until equipment operation ceases; the Nicad battery volts stabilise at about 1.0 V per cell and bleeps continue until the VS+- power lead is reconnected to commence a new recharge and restart operation or the equipment is switched OFF.    A rechargeable battery management module substantially as described herein with reference to Figures 1-4 of the accompanying drawing.