NOVELTY - A semiconductor structure is fabricated by depositing a first layer of compositionally graded silicon germanium buffer, first etch-top silicon germanium layer and second etch-stop layer of strained silicon.    USE - Various electronics and optoelectronics applications, e.g. in semiconductor device such as metal oxide semiconductor field effect transistor (MOSFET) device, MESFET device, solar cell device and optoelectronic device applications (claimed).    ADVANTAGE - The process provides a relaxed SGOI substrate with high Ge composition and wide range of Ge compositions. It also provides improved strained-Si or strained-SiGe FET devices on SGOI substrate with high Ge composition.    DETAILED DESCRIPTION - Fabrication of a semiconductor structure involves:    (1) providing a first semiconductor substrate, where the Ge composition x is increasing from 0-20% and a portion of the buffer with Ge composition larger than 20% forms a natural SiGe etch-stop layer;    (2) depositing a graded silicon germanium (Si1-xGex) buffer on the first semiconductor substrate;    (3) depositing material layers such as relaxed Si1-yGey layer, strained Si1-zGez layer, strained-silicon, germanium, gallium arsenide, III-V materials, and II-VI materials, where germanium compositions y and z are at 0-1;    (4) bonding the deposited layers to a second substrate;    (5) removing the first substrate to explore the etch-stop SiGe layer which include a portion of the compositionally graded Si1-xGex buffer where the Ge composition is larger than ca. 20%; and    (6) removing the remaining portion of the compositionally graded Si1-xGex buffer in order to release the materials layers.    An INDEPENDENT CLAIM is included for an etch-stop layer structure that includes a monocrystalline semiconductor substrate, comprising:    (1) a first compositionally graded Si1-xGex buffer;    (2) a uniform etch-stop Si1-yGey layer of with a selected thickness; and    (3) a second compositionally graded Si1-zGez buffer.    DESCRIPTION OF DRAWING(S) - The figures show flow process diagrams of a SGOI substrate fabrication process and a block diagram of relaxed SiGe and strained-Si regrowth on a relaxed SGOI substrate for strained-Si MOSFET applications.