NOVELTY - Making back-contact solar cell involves: forming several holes (30) extending from front surface (15) of semiconductor substrate (10) of first conductivity, to rear surface; forming diffusion (20) of opposite conductivity on front and rear surfaces, and surfaces enclosing holes; depositing patterned dielectric layer (18) on rear surface; alloying contacts (90) of first conductivity type with substrate; disposing first conductive grid (70) on dielectric layer in electrical contact with contacts; and disposing second conductive grid on rear surface in electrical contact with diffusion.    USE - For making back-contact solar cell (claimed).    ADVANTAGE - The methods provide improved methods for forming back-contact solar cells by low-cost process sequence; by providing rear surface contact structure for the cells comprising wide grid lines for increased conduction combined with minimum p-type contact areas and maximum n-type diffusion for increased efficiency; while electrically isolating negative and positive polarity grids and junctions. The processes have fewer, more economical process steps and produce high efficiency solar cells with more efficient configurations of rear surface contacts and grids. The processes can be employed to eliminate need for patterning of n+ diffusion on rear surface of cell, thus provides higher conversion efficiency. The region with exposed p-type surface on rear (n+p structure) has lower energy conversion efficiency than region with n+ diffusion on rear surface (n+pn+ structure) that has higher conversion efficiency as photogenerated carriers can be collected at n+ junction on either surface. Thus it is advantageous to minimize p-type surface area on rear of the cell. In addition, as p-type surface must be well passivated to achieve maximum efficiency, passivation layers on p-type surface must be of high quality and relatively free of defects, which is difficult and expensive to achieve. By minimizing this area, need for any passivation is greatly reduced, or even eliminated, which results in cost savings due to reduction in process steps. The method is also applicable if wafer of either conductivity type is used. In method screen printing to pattern the n+ diffusion can be used. P-type silicon wafer comprises n+ diffusion on entire front cell surface and walls of hole. Dielectric layer is disposed on front cell surface to passivate surface and provide anti-reflection coating. The n+ diffusion surrounding via on rear surface forms high efficiency n+pn+ region, adjacent to which n-type contact and grid is disposed. The remainder of rear surface forms n+p region (p-type surface). P-type contact and grid is disposed adjacent to p-type surface. The emitter wrap through (EWT) solar cell with Al-alloyed contact manufactured by the method has higher conversion efficiency, as most of the rear surface is covered with high-efficiency n+ diffusion. The aluminum alloy forms heavily doped p-type contact that compensates n+ diffusion to allow contact with p-type silicon base. The aluminum or aluminum alloy reacts with silicon above eutectic temperature. Printed p-type contact and grid comprising silver, cover Al-alloyed contact to carry current to cell edges. The grid is electrically isolated from n+ diffusion by use of dielectric passivation layer, preferably comprising nitride. P-type contacts can be made small enough so that most of cell has high-efficiency n+pn+ structure. The percentage of total rear surface area occupied by p-type contacts is (less than 30, preferably less than 20, especially less than 10)%. Metallization barrier permits use of large p- and n-type grids to improve conductivity and efficiency by reducing metallization areas and surface recombination velocity.    DETAILED DESCRIPTION - Method for making back-contact solar cell, involves: forming several holes (30) extending from front surface (15) of semiconductor substrate (10) to rear surface of substrate, where substrate comprises first conductivity type; providing diffusion (20) comprising opposite conductivity type on front surface, rear surface, and on surfaces enclosing holes; depositing patterned dielectric layer (18) on rear surface; alloying several contacts (90) comprising first conductivity type with substrate; disposing first conductive grid (70) on dielectric layer in electrical contact with contacts; and disposing second conductive grid on rear surface in electrical contact with diffusion. The diffusion is lightly doped. The step of alloying several contacts is performed through existing regions of dielectric layer, or is performed after removing regions of dielectric layer to expose regions of rear surface. The contacts occupy (less than 30, preferably less than 20, especially less than 10)% of area of rear surface. The substantially all of portions of rear surface not occupied by contacts comprise diffusion. The material comprising second conductive grid at least partially fills holes. The width of grid line of first conductive grid is wider than width of contact. The first conductive grid is interdigitated with second conductive grid. The at least one of the first or second conductive grids comprise grid lines having tapered width. The method alternatively involves: forming several holes (150) extending from front surface of semiconductor substrate (120) to rear surface of substrate, where substrate comprises first conductivity type; depositing patterned diffusion barrier on rear surface; providing diffusion (140) comprising opposite conductivity type on front surface, first regions of rear surface not covered by diffusion barrier, and surfaces enclosing holes; removing diffusion barrier; depositing metallization barrier (180) comprising first openings smaller than first regions and aligned with holes and second openings aligned with and smaller than second regions of rear surface that had been covered by diffusion barrier, on rear surface, disposing first conductive grid (110) partially on metallization barrier and in electrical contact (100) with diffusion through first openings, and disposing second conductive grid partially on metallization barrier and in electrical contact (160) with substrate through second openings.    DESCRIPTION OF DRAWING(S) - The figures show cross-section of emitter wrap through (EWT) solar cell showing side view through hole and perpendicular to grid lines, with aluminum-alloyed contacts to p-type substrate; and cross-section of silicon solar cell utilizing increased emitter coverage area on backside by use of dedicated metallization barrier.    P-type silicon wafer substrate (10, 120)    Front cell surface of substrate (15)    Dielectric layer (18)    Diffusion of n+ type (20, 140)    Holes (30, 150)    P-type grid (70, 110)    Dielectric passivation layer (80)    P-type contact (90, 100)    Passivation/anti-reflection layer (145)    N-type contact (160)    Metallization barrier (180)