NOVELTY - Forming crystalline silicon solar cell (611) involves: forming vias of two different diameters (602, 603) through crystalline silicon substrate (600) from first surface to second surface; depositing first silicon layer (604) on first surface of crystalline silicon substrate and on surfaces within vias, which fills vias of lesser diameter; depositing second silicon layer (605) over first silicon layer, which fills vias of greater diameter; depositing third silicon layer (606) over second silicon layer; and depositing metallization layer on second surface of crystalline silicon substrate.    USE - For forming crystalline silicon solar cell (claimed).    ADVANTAGE - The method involves making crystalline silicon solar cells by utilizing silicon substrate that is low purity upgraded metallurgical grade (UMG) silicon substrate and is less expensive to manufacture than high purity polysilicon, such that less expensive processes can be used to purify the metallurgical grade silicon, and lowers the cost of making solar cells; as compared to the prior art manufacturing of solar cells by using high purity polysilicon that is obtained by purifying metallurgical grade silicon (MG-Si) using Siemens process to remove boron and phosphorus impurities, which is very expensive and accounts for major component of cost of wafers used to form crystalline silicon solar cells. The method involves depositing amorphous silicon (such as p- and n-type layer(s)) on crystalline silicon substrate with substrate vias or through holes of varying diameters, annealing stack of amorphous silicon layers to cause solid phase epitaxial conversion, and metalizing substrate assembly using standard metallization techniques. The first layer of amorphous silicon fills substrate vias having smaller diameter while second layer of amorphous silicon fills substrate vias of larger diameter. In solar cell, the second deposited silicon layer acts as active part of solar cell. Consequently, it is possible to use as starting substrate the UMG silicon having high concentration of boron or phosphorus of 1x 1016 to 1x 1019 atoms/cm3, which is typically not tolerated by solar cells that use substrate itself for photovoltaic activity. A sufficient number of larger sized vias are made to obtain sufficient contact area with reflective metal, such as aluminum, to obtain good current flow from solar cell to backside metal. Also, it is advantageous to increase contact area i.e. number of vias, so as to increase reflected radiation from metal that increases charge carrier generation and collected current. The reflection by back metal, such as aluminum, can be increased by increasing number of substrate vias. The larger diameter substrate vias are made slightly larger so that second amorphous silicon layer is not able to fill up substrate vias, and subsequently deposited third layer of amorphous silicon of different conductivity than second silicon layer is able to reach back surface of substrate through larger diameter vias. In this configuration, since both second and third silicon layers are available at back of substrate, inter-digitated back contact (IBC) metallization techniques can be used to make cell contact, and no metallization is needed on the front. The larger diameter substrate vias are made even larger so that neither first, second nor third layers of amorphous silicon is able to fill up substrate vias; and allows for back contact metallization.    DETAILED DESCRIPTION - Forming crystalline silicon solar cell (611) involves: forming vias of two different diameters (602, 603) through crystalline silicon substrate (600) from first surface to second surface; depositing first silicon layer (604) on first surface of crystalline silicon substrate and on surfaces within vias, where the first silicon layer fills vias of lesser diameter; depositing second silicon layer (605) over first silicon layer, where second silicon layer fills vias of greater diameter; depositing third silicon layer (606) over second silicon layer; and depositing metallization layer on second surface of crystalline silicon substrate. The method further involves depositing passivation layer on third silicon layer prior to depositing metallization layer on second surface and forming metal contacts on selected areas of the third silicon layer; annealing crystalline silicon substrate, prior to depositing metallization layer, at temperature sufficient to cause crystallization of first, second and third silicon layers and to electrically activate dopants in layers; and removing saw damage from substrate surfaces and texture etching crystalline silicon substrate prior to forming vias. The crystalline silicon substrate is p-type silicon substrate, first silicon layer is p+-type amorphous silicon layer, second silicon layer is p-type amorphous silicon layer, and third silicon layer is n+-type amorphous silicon layer. The crystalline silicon substrate is upgraded metallurgical grade crystalline silicon substrate having concentration of boron or phosphorus of 1x 1016 to 1x 1019 atoms/cm3. The vias are formed by laser ablation. The vias of two different diameters comprise first via having diameter of 4-15 microns, and second via having a diameter of 40-60 microns. The second silicon layer is 20-30 microns thick. The method alternatively involves forming vias of two different diameters through a crystalline silicon substrate from first surface to second surface; depositing first silicon layer over first surface of crystalline silicon substrate and on surfaces within vias, where first silicon layer fills vias of lesser diameter; depositing second silicon layer over first silicon layer; depositing third silicon layer over second silicon layer, where vias of greater diameter remain open after deposition of first, second and third silicon layers; depositing passivation layer over second surface of crystalline silicon substrate; patterning passivation layer to expose regions of first silicon layer and third silicon layer; and depositing conductive layer over patterned passivation layer so that conductive layer contacts exposed regions of first silicon layer in vias of lesser diameter and third silicon layer in vias of greater diameter.    DESCRIPTION OF DRAWING(S) - The figure shows schematic cross-sectional view of the solar cell substrate during different stages in processing sequence.    Crystalline upgraded metallurgical grade silicon substrate (600)    Substrate vias (602, 603)    Amorphous p+-type silicon layer/first silicon layer (604)    Amorphous p-type silicon layer/second silicon layer (605)    Amorphous n+-type type silicon layer/third silicon layer (606)    Passivation layer (607, 610)    Conducting layer (609)    Solar cell (611)