NOVELTY - The method comprises forming (520) an insulation layer directly on a silicon wafer, forming (510) planar by-pass diodes integral with the silicon wafer and the insulation layer, bonding (530) a single crystal layer of a compound consisting of germanium based compounds, II-IV semiconductor compounds or III-V semiconductor compounds using plasma assisted electrostatic bonding directly to the insulation layer, wafer cleaving (540) the single crystal layer to obtain a crystal layer of desired thickness and an excess layer, and forming (560) multi-junction layers on the insulation layer.    USE - The method is useful for making a solar cell circuit for space missions.    ADVANTAGE - The method ensures unique, simple and economical manufacture of solar cell circuit on lightweight silicon wafer with high voltage capability and less array assembly mass and simple power management and without any processing waste.    DETAILED DESCRIPTION - The method comprises forming (520) an insulation layer directly on a silicon wafer, forming (510) planar by-pass diodes integral with the silicon wafer and the insulation layer, bonding (530) a single crystal layer of a compound consisting of germanium based compounds, II-IV semiconductor compounds or III-V semiconductor compounds using plasma assisted electrostatic bonding directly to the insulation layer, wafer cleaving (540) the single crystal layer to obtain a crystal layer of desired thickness and an excess layer, and forming (560) multi-junction layers on the insulation layer to fabricate a multi-junction solar cell circuit between the planar by-pass diodes. The formation of the planar by-pass diodes is epitaxial growth of the diode into the insulation layer and diffusion of P+ and N- dopants into the silicon wafer. The method further comprises forming a monolithic interconnected module structure to electronically interconnect the multi-junction solar cell circuits on the silicon wafer through positive contacts and negative contacts electronically connected with the by-pass diodes, forming a blocking diode on an edge opposite of the planar by-pass diode on a first multi-junction solar cell circuit in the multi-junction solar cell circuits, and utilizing the excess layer for manufacture of another of the solar cell circuits. The planar by-pass diodes comprise a position at an edge of each of the multi-junction solar cell circuits. The multi-junction solar cell circuit comprises a triple junction. The triple junction solar cell circuit comprises a first junction having base and emitter layers, a second junction having base and emitter layers, and a third junction having base and emitter layers.    DESCRIPTION OF DRAWING(S) - The figure shows a flow diagram of a process for manufacturing solar cell circuits.    Forming diodes in a silicon based wafer (510)    Forming an insulation layer on the wafer (520)    Bonding a thick layer of germanium to the insulation layer (530)    Wafer leaving the single crystal layer (540)    Forming multi-junction layer. (560)