TECHNOLOGY FOCUS - ELECTRICAL POWER AND ENERGY - Preferred Method: In the method above, selectively etching the sacrificial porous silicon layer to form a released crystalline silicon layer comprises treating the composite wafer to an aqueous etchant maintained at 0-10 degrees C. The aqueous etchant comprises one or more of potassium hydroxide, sodium hydroxide and hydrogen fluoride. The aqueous etchant further comprises a surfactant. The aqueous etchant further comprises an alcohol, where the alcohol is isopropyl alcohol. The method further comprises treating the composite wafer and the aqueous etchant with ultrasonic energy. Forming a crystalline silicon layer comprises epitaxially growing the crystalline silicon layer using chemical vapor deposition. The sacrificial porous silicon layer comprises a material selected from a carbon doped oxide, a spin-on-glass (SOG) and fluoridated silicon glass (FSG). The crystalline silicon layer is a p-doped crystalline silicon layer. Making a solar cell comprises forming a sacrificial porous silicon layer on a crystalline wafer; growing a silicon-based device layer on the sacrificial porous silicon layer; etching the sacrificial porous silicon layer to release at least a portion of the silicon device-based layer; and attaching the released portion of the silicon-based device layer to form the solar cell. Etching the sacrificial porous silicon layer to release the portion of the silicon-based device layer comprises treating the sacrificial porous silicon layer to an aqueous etchant at 0-10 degrees C. The method further comprises treating the composite wafer and the aqueous etchant to ultrasonic energy. Growing the silicon-based device layer on the sacrificial porous silicon layer comprises epitaxially growing the silicon device layer using chemical vapor deposition. Making a solar cell comprises forming a composite wafer comprising a crystalline silicon wafer, a crystalline silicon device layer, and a sacrificial porous silicon layer sandwiched between the crystalline silicon wafer and the silicon device layer; and etching the sacrificial porous silicon layer with an aqueous etchant to release the crystalline silicon device layer, where the aqueous etchant is maintained at 0-10 degrees C.