TECHNOLOGY FOCUS - ELECTRICAL POWER AND ENERGY - Preferred Components: The average grain size of each of the PV layers is 1-60 nm, and a deposition thickness of each of the PV layers is less than 1000 nm, (preferably less than 500 nm), where an average grain size of the PV layers varies across along a deposited thickness of the PV layers. In the PV structure: the array of PV nanostructures is arranged in a brush configuration; the nanocables are metallic and elongated, comprises nickel and have uniform peripheries and longitudinal lengths; the PV layers exhibit physical characteristics of pulse plating or reverse pulse plating, where one of the PV layers is plated p-type cadmium telluride; a heterojunction is formed between the PV layers; a depletion region of the PV layers extends across a full thickness of the PV layers; and the nanostructures have smaller top diameters or widths than bottom diameters or widths. The PV structure further comprises: a power inverter formed on the same substrate as the array; an upper conductive layer above the PV layers, where the upper conductive layer comprises a dopant that increases an electrical conductivity of the upper conductive layer, a doped conductive oxide, or an undoped layer closest to the PV layers; a passivation layer between the upper conductive layer and the PV layer closest to it; an interfacial layer that forms a rectifying junction between the PV layers; and a back contact layer forming an interface between the conductive nanocables and the PV layer closest to it, where the back contact layer is a metallic film that assists in adjusting a Fermi level and band bending of the interface to improve voltage open circuit for the PV structure and enhances adhesion of the PV layer to the conductive nanocable. The PV layers comprise a material containing II-VI, preferably III-V p- or n-type materials i.e. amorphous silicon (preferred), cadmium telluride, cadmium sulfide, gallium arsenide or copper indium gallium selenium. The PV structure is constructed on: a substrate containing a 200 mm, 300 mm or 450 mm silicon wafer; a substrate of flat panel display glass; a flexible substrate; or a glass substrate. The device further comprises an interfacial layer that enhances the rectifying junction between the III-V and II-VI compound semiconductors, where the II-VI compound is a cadmium telluride or its alloy, or a doped composition of cadmium telluride, and the III-V compound is a gallium nitride (gallium aluminum nitride) or its alloy, or a doped composition of gallium nitride. The interfacial layer comprises an oxide, where the oxide is: a doped tin oxide which is zinc-doped tin oxide or cadmium-doped tin oxide; or a doped zinc oxide which is a cadmium zinc oxide. In the device: a depletion region of the first and second semiconductor layers extends across a full thickness of the semiconductor layers; and the nanostructures containing the nanocables and semiconductor layers have smaller top diameters or widths than bottom diameters or widths. Preferred Method: In the method (M1): at least one of the PV layers is formed by pulse plating or reverse pulse plating, where a duty cycle of the pulse plating has an on time of greater than 70%, preferably 90%, or an on time of less than 70%, preferably 30%, or an on time of 30-70%, or plating p-type cadmium telluride at a bath temperature of less than 70 degrees C; adding the PV layers above the nanocables comprises plating p-type cadmium telluride; and an n-type PV layer is formed above a p-type PV layer. The method (M1) further comprises: sonicating the plating bath during the plating; forming a power inverter on the substrate; cleaning the p-type layer prior to forming the n-type layer over it; etching the p-type layer prior to forming the n-type layer over it; performing a thermal diffusion activation step; passivating a grain boundary of the PV layers, where the step of passivating includes application of at least one chloride to the PV layers; forming the upper conductive layer above the PV layers and a passivation layer between the upper conductive layer and the PV layer closest to it, where the step of forming an upper conductive layer above the PV layers comprises doping a layer with conductive material for increasing the electrical conductivity of it; and forming a back contact layer above the nanocables for forming an interface between the conductive nanocables and the PV layer closest to it, where the back contact layer is a metallic film that assists in adjusting a Fermi level and band bending of the interface to improve voltage open circuit for the PV structure and enhances adhesion of the PV layer to the conductive nanocable. The method (M2) further comprises adjusting a presentation angle of the array relative to a light source position for further increasing an observable power output of the array. The method (M3) further comprises depositing an interfacial layer between the first semiconductor layer and the second semiconductor layer to enhance the rectifying junction between the III-V and II-VI compound semiconductors.