NOVELTY - The memory device comprises an array (200) of memory structures disposed in rows and columns and constructed over a substrate, word lines connected to a first signal electrode (212) of a row of memory cells (220), and bit lines connected to a second signal electrode (216) of a column of memory cells. Each memory structure further comprises a resistive layer coupled to the first and second signal electrodes. The resistive layer forms transistors, comprises memory elements and stacked layers, and is spin-coated over the substrate.    USE - The memory device is useful in an electronic device (claimed) including photovoltaic (solar) cell (from drawings), personal computer, networking system and wireless communications-product.    ADVANTAGE - The memory device is compact, power efficient and dense, and enhances density and speed advantages of the integrated circuit in accordance with Moore's Law.    DETAILED DESCRIPTION - The memory device comprises an array (200) of memory structures disposed in rows and columns and constructed over a substrate, word lines connected to a first signal electrode (212) of a row of memory cells (220), and bit lines connected to a second signal electrode (216) of a column of memory cells. Each memory structure further comprises a resistive layer coupled to the first and second signal electrodes. The resistive layer forms transistors, comprises memory elements and stacked layers, and is spin-coated over the substrate. A driver circuit is arranged for selectively controlling the first signal electrodes or the second signal electrodes. The circuit includes Y gate, a sense amplifier, an input-output buffer, an X address decoder, a Y address decoder, and an address buffer. The substrate is a silicon-on-insulator wafer. The resistive layer store data at intersections of resistors. An array of redundant memory elements including a row or a column of redundant resistive-elements are arranged in the memory device. Magnetic elements or optical elements are coupled to the memory. The memory device forms a memory hierarchy to optimize data access speed. An INDEPENDENT CLAIM is included for an electronic device comprising a memory.    DESCRIPTION OF DRAWING(S) - The diagram shows a schematic view of a memory device comprising nano elements.    Memory structure array (200)    First signal electrode (212)    Second signal electrode (216)    Memory cells (220)    First driver circuit (250)    Second driver circuit. (252)