TECHNOLOGY FOCUS - ELECTRONICS - Preferred Method: In making a semiconductor structure, the front amorphous doping is controlled to create a front layer doping with a doping profile. The front amorphous doping profile is a profile with at least one step change in doping level. In the method, the thermal budget temperature is 700 degrees C, preferably below 600 degrees C. The thermal budget temperature is a rapid thermal processing temperature, where the temperature is less than 900 degrees C and the time of temperature application is less than 90 seconds, preferably less than 30 seconds. The substrate is made of silicon, silicon on glass, silicon on sapphire, silicon on quartz, silicon on metal, silicon on graphite, silicon on ceramic, a silicon and germanium compound, metallurgical grade silicon, solar grade silicon, germanium, germanium on glass, germanium on sapphire, germanium on quartz, germanium on metal, germanium on graphite, and germanium on ceramic, glass, metal, ceramic, graphite, or plastic. The front amorphous semiconductor layer is silicon, germanium, a compound of silicon and germanium, or a compound of silicon and carbon. The method further comprises depositing a front passivation layer on the front doped crystalline semiconductor layer. The front passivation layer is deposited by low temperature anodic oxidation, depositing plasma enhanced chemical vapor deposition (PECVD) amorphous silicon with hydrogen, depositing a thin film by either atomic layer deposition (ALD), evaporation, low pressure chemical vapor deposition (LPCVD), or PECVD. The method further comprises depositing an antireflective coating on the front passivation layer, where the antireflective coating is deposited by sputtering, spray-coating, spin coating, PECVD, LPCVD, or spin-on followed by a low temperature anneal. The method further comprises providing openings in the front passivation layer and antireflective layer; and attaching one or more first conductive contact to substrate through the openings in the antireflective layer and attaching one or more second conductive contacts to the front doped crystalline semiconductor layer through the openings in the passivation layer. The first conductive contacts and the second conductive contacts are attached using one or more of the following: evaporation, screen printing, laser printing, and a process performed below 700 degrees C. The front doped crystalline semiconductor layer is crystallized to have a grain size larger than 1 micron. It is crystallized to form a single crystal or a multicrystalline layer. Making a semiconductor structure comprises: (a) depositing a front amorphous semiconductor layer on a front side of a semiconductor substrate, where the front amorphous semiconductor layer has a front amorphous doping and the substrate having a substrate doping; (b) crystallizing the front amorphous semiconductor layer into a front doped crystalline semiconductor layer by applying heat at a low thermal budget temperature; and (c) depositing an amorphous silicon layer on the front doped crystalline semiconductor layer on an amorphous side of the doped crystalline semiconductor layer that is opposite the substrate, where the amorphous silicon layer has an amorphous doping, the layer doping and the amorphous doping is at levels so that a tunnel junction is formed between the front doped crystalline semiconductor layer and the amorphous layer. Making a semiconductor structure comprises: (a) depositing a front amorphous semiconductor layer on a front side of a semiconductor substrate, where the front amorphous semiconductor layer has a front amorphous doping and the substrate having a substrate doping; (b) depositing a back amorphous semiconductor layer on a back side of the semiconductor substrate, where the back amorphous semiconductor layer has a back amorphous doping and the substrate having a substrate doping; and (c) crystallizing the front amorphous semiconductor layer into a front doped crystalline semiconductor layer and the back amorphous semiconductor layer into a back doped crystalline semiconductor layer by applying heat at a low thermal budget temperature, where the front doped crystalline semiconductor layer has a front layer doping and the back doped crystalline semiconductor layer having a back layer doping.