NOVELTY - A chip package (10) comprises semiconductor chip(s) (100) having conductive pads (100a); first redistribution layers (RDLs) (206) electrically connected to conductive pads; a single-layer insulating structure (208) covering the semiconductor chip, and having first openings (208a) exposing the first RDLs; second RDLs (210) electrically connected to first RDLs; a first passivation layer (212) having second openings (212a) exposing the second RDLs; and conductive bumps (214) electrically connected to the second RDLs.    USE - Chip package used for electronic components with active or passive elements, or with digital or analog integrated circuits. Uses include but are not limited to optoelectronic devices, microelectromechanical systems, microfluidic systems, physical sensors for detecting physical characteristics such as detecting heat, light, or pressure, image sensor devices, LEDs, solar cells, radio frequency circuits, surface acoustic wave devices and gyroscopes.    ADVANTAGE - The conductive bumps may be formed above the carrier substrate and outside of the semiconductor chip through the fan-out type RDLs except that the conductive bumps is disposed directly above the semiconductor chip. That is, the terminal contact regions of the chip package are not limited to the region directly above the semiconductor chip, so the number of terminal contact regions can be increased, thus meeting the package demands of high performance chips. As the semiconductor chip is mounted onto the carrier substrate, the chip shift is effectively controlled by the skidproof structure surrounding the semiconductor chip and on the carrier substrate, thus maintaining or improving the yield of chip packages. Additionally, the single-layer insulating structure may be used as a fill material between two semiconductor chips and simultaneously act as a passivation layer for covering the RDLs, thus simplifying the fabrication and reducing the fabrication cost.    DETAILED DESCRIPTION - A chip package (10) comprises:    (A) a carrier substrate (200), which is a raw silicon substrate;    (B) semiconductor chip(s) (100) disposed on the carrier substrate, and having conductive pads (100a);    (C) first redistribution layers (RDLs) (206) disposed on semiconductor chip and electrically connected to the conductive pads;    (D) a single-layer insulating structure (208) disposed on carrier substrate, covering the semiconductor chip, and crossing the first RDLs, and having first openings (208a) exposing the first RDLs;    (E) second RDLs (210) disposed on the single-layer insulating structure and electrically connected to the first RDLs through the first openings;    (F) a first passivation layer (212) disposed on single-layer insulating structure and the second RDLs and having second openings (212a) exposing the second RDLs; and    (G) conductive bumps (214) correspondingly disposed in the second openings and electrically connected to the second RDLs.    The chip package further comprises a skidproof structure (202) disposed on the carrier substrate. An INDEPENDENT CLAIM is included for fabrication of a chip package.    DESCRIPTION OF DRAWING(S) - The drawing is a cross-sectional view of a method for fabricating a chip package.    Chip package (10)    Semiconductor chip (100)    Conductive pads (100a)    Carrier substrate (200)    Skidproof structure (202)    First RDL (206)    Single-layer insulating structure (208)    First openings (208a)    Second RDL (210)    First passivation layer (212)    Second openings (212a)    Conductive bumps (214)