TECHNOLOGY FOCUS - ELECTRONICS - Preferred Components: The substrate is a single-crystal substrate. The single-crystal substrate comprises a hexagonal crystal lattice. In the oxide material: where up to one-half of sites for the lithium cations in the oxide composition are vacant such that the oxide composition exhibits p-type conductivity; where up to 10% of oxygen anion sites at the corners of the octahedra are vacant such that the oxide composition exhibits n-type conductivity. The p-type conductivity is greater than 1000 Siemens per centimeter. The n-type conductivity is greater than 1000 Siemens per centimeter. The oxide material comprises two or more single crystal epitaxial layers of the oxide composition disposed on the surface of the substrate. The B1 cations of the two or more oxide compositions are different for each of the two or more single-crystal epitaxial layers. The oxide composition exhibits a conductivity exceeding 1000 Siemens per centimeter in either n-type or p-type configurations. The oxide composition exhibits a minority carrier lifetime exceeding 1 microsecond.    TECHNOLOGY FOCUS - INORGANIC CHEMISTRY - Preferred Components: The crystal structure of the oxide composition has a same structure as alpha -sodium orthoferrite ( alpha -NaFeO2). Preferred Method: The method of fabricating oxide material further comprises growing an additional single-crystal epitaxial layer of the oxide composition on a surface of the grown oxide composition. In the method of fabricating oxide material, where the additional single-crystal epitaxial layer of the oxide composition has a B1 cation that is different than the B1 cation of the oxide composition on which the additional single-crystal epitaxial layer is grown. The growing comprises molecular beam epitaxy. The precursor of the B1 cation is halide composition. The method of splitting water, further comprises: separating the hydrogen gas from the water; and collecting the separated hydrogen gas.    TECHNOLOGY FOCUS - INSTRUMENTATION AND TESTING - Preferred Components: The first layer and the second layer are formed with the metal oxide semiconductor materials. The first layer and the second layer are formed with lithium niobite. (I) further comprises: a first electrode in electrical communication with the first layer and a second electrode in electrical communication with the second layer, the first and second electrodes being the electrical charge source; and a third layer of a third variable resistance material defining a third surface, the third variable resistance material being programmable to be one of an n-type or a p-type material, the third layer being positioned proximate the second layer to form a second interface boundary and also being in electrical communication with the charge source. In (I): the first and second layers are formed in at least one of a polygonal or circular shape; the first and second layers are doped at varying density levels; the electrical charge source is a radial electrode disposed to apply an electric charge between an inner electrode and an outer electrode, the radial electrode being positioned on the first layer; and the first and second layers comprise ions/dopants that flux in response to the charge from the electric charge source. In (II): the first and the third epitaxial metal layers being formed of a first material and the second epitaxial metal layer being formed of a different material so that the metal-oxide semiconductor region is a symmetric heterostructure; the first and second electrodes are configured to apply an electric potential across the metal-oxide semiconductor region to enable ion/dopant flux across the first and second boundary interfaces; the first, second and third epitaxial layer are sized and shaped to have at least one of a polygonal or circular cross-section, sized and shaped in a vertical column that is tapered toward the first electrode and sized and shaped with a geometry configured to constrict ion and electric current flow; the first epitaxial layer consists only of lithium niobite, the second epitaxial layer consists only of lithium cobaltate, and the third epitaxial layer consists only of lithium niobite or the first epitaxial layer consists only of lithium cobaltate, the second epitaxial layer consists only of lithium niobite and the third epitaxial layer consists only of lithium cobaltate; the first doped level and the third doped level have a positive charge and the second doped level has a negative charge or the first doped level and the third doped level have a negative charge and the second doped level has a positive charge; and the first, second and third epitaxial layer are doped at varying density levels. The first and second layers in (I), the metal-oxide semiconductor region in (II) are and the variable resistance pillars in (III) forms, part of at least one of a memory cell, memristor (600), memdiode, memtransistor or charge storage device. (II) further comprises a dielectric/ferroelectric material situated on a portion of the metal-oxide-semiconductor region and intermediate the first and second electrodes, and further comprises a third electrode situated in electrical communication with the dielectric/ferroelectric material. In (III), the array of variable resistance pillars comprise up to three layers of epitaxial-metal-oxide semiconductor materials, and each of the pillars are one of symmetric heterostructures and symmetric heterostructures, and each of the three layers is a lithium based metal oxide semiconductor. (III) further comprises a network of read/write access lines configured to be in communication with each of the array of variable resistance pillars to enable detection and programming of a resistance value for each of the array of variable resistance pillars. In (III): the array of variable resistance pillars can write and erase a resistance value without application of a set/reset voltage; the array of variable resistance pillars have a length of 10-100 microns; one of the electrodes is positioned proximate the substrate and between at least one of the pillars and the other electrode is positioned proximate an opposing end of the pillars and where the distance between the electrodes is greater than 10 microns; the array of variable resistance pillars have a ratio of programmable resistance values equal to or exceeding 1000:1 from a maximum resistance value to a minimum resistance value; and each of the variable resistance pillars forms part of a memory cell, with each memory cell having an infinite number, preferably more than two data states. (IV) further comprises: a second layer of a second variable resistance material, the second variable resistance material being programmable to be one of an n-type or a p-type material, a third layer of a third variable resistance material; the third variable resistance material being programmable to be one of an n-type or a p-type material, the second and third layers stacked on the first layer and in electrical communication to receive electric potential from the electrical charge source and in response transporting holes and electrons for programming resistances for the second and third variable resistance materials; and a second layer of semiconductor material that is programmed to be a memtransistor, and where the first layer is formed to be a memtransistor, and where the memtransistor are arranged in a complementary fashion to form a complementary memtransistor, where the first layer comprises many sublayers so that the first layer has at least two heterojunctions with ion sources and ion sinks and where the device includes source, gate, drain electrodes, where the application of voltage to the source, gate, drain electrodes adjust the conductivity of the sublayers and programs the device to be put into a determined operational state. In (IV), the first, second and third layer are configured to be programmable to be programmed to an N-type transistor or a P-type transistor in response to charges provided by the electrical charge source, where a direct current (DC) voltage is applied the electrical charge sources for programming; first, second and third layer are held in the programmed state by using an alternating current (AC) source for data readout and processing operations; the first layer comprises many sub-layers and where boundaries between the sub-layers form boundary interfaces, and where in response to electric potential the sub-layers source or sink ions/dopants to vary the resistance of the first layer; the electrical charge source is a solar cell configured to convert light into an electric potential for delivery to the first layer; and the layer is programmable to be at least one of devices (a one transistor memristance programmed memory element, a transistor whose gain can be adjusted via memristance effects, a heterojunction transistor in the AMO2 semiconductor family and a single transistor that can be reconfigured through application of appropriate source/drain/gate voltages to produce any combination of n-channel metal-oxide-semiconductor (NMOS) depletion mode, NMOS enhancement mode, positive channel metal-oxide-semiconductor (PMOS) depletion mode and PMOS enhancement mode electronic behavioral first layer). In (V): the solar cell and the crystalline-lithium based semiconductor material are integrated in a single package; the crystalline-lithium based semiconductor material comprises many sublayers of crystalline-lithium based layers having alternating n-type and p-type charges; the device has a charging state of operation, where the crystalline-lithium-based semiconductor material retains charge due to lithium ion movement in response to receiving electric potential from the solar cell and has a discharging state, where lithium ions move within the crystalline-lithium based semiconductor material to source an electrical charge; and the crystalline-lithium based semiconductor material comprises at least one surfaces configured to receive light energy and generate an electric potential. Preferred Definitions:    B1 = Nb, Co or combination of Nb and at least one of Fe, Co or Ni.    EXAMPLE - No suitable example given.