NOVELTY - The semiconductor device (10) comprises a p-type oxide layer (13) formed of oxide consisting of a copper (Cu)-containing copper monoxide, a tin (Sn)-containing Sn monoxide, a copper tin oxide containing a Cu-Sn alloy and a nickel (Ni) tin oxide containing a Ni-Sn alloy, and a substrate formed of glass, a metal, silicon, a polymer and cellulose paper. The p-type oxide layer: has an amorphous structure, a nano-crystalline structure, or a polycrystalline structure; is formed of impurities of 0.2 wt.% to control hole carriers; and has nonconductor, conductor, or semiconductor characteristics.    USE - The semiconductor device such as a complementary metal-oxide-semiconductor device, a thin-film transistor, a heterojunction device, a logic gate, a PN junction device, a metal-insulator semiconductor junction device, a LED device, an optical sensor and a p-type field-effect transistor (all claimed) is useful for electronic devices, photoelectronic devices, semiconductor industries, flat panel displays, logic circuit devices, sensors, medical and bio devices, micro/nano-electronic industries, field-effect devices such as switches or amplifiers, data-oriented circuits, displays, logic circuits such as inverter logic gates, AND-OR logic gates, and NAND-NOR logic gates, ring oscillators, shift registers, radio-frequency identifications, smart labels, smart apparatuses including safety transparent electronic devices and sensors, apparatus manufacturing industries, medical and/or food industries, such as medical components, control circuits, and signal switching circuits, national defense industries such as stealth techniques and transparent display devices, solar cells, biotechnology and nano-electronic devices.    ADVANTAGE - The semiconductor device can be easily, effectively and economically manufactured with high electric conductivity and rectifying characteristics.    DETAILED DESCRIPTION - The semiconductor device (10) comprises a p-type oxide layer (13) formed of oxide consisting of a copper (Cu)-containing copper monoxide, a tin (Sn)-containing Sn monoxide, a copper tin oxide containing a Cu-Sn alloy and a nickel (Ni) tin oxide containing a Ni-Sn alloy, and a substrate formed of glass, a metal, silicon, a polymer and cellulose paper. The p-type oxide layer: has an amorphous structure, a nano-crystalline structure, or a polycrystalline structure; is formed of impurities of 0.2 wt.% to control hole carriers; has nonconductor, conductor, or semiconductor characteristics according to oxygen (O) content; is a p-type semiconductor layer of a p-n junction device; and is a channel layer, a source electrode, a drain electrode, or a semiconductor layer of the semiconductor device. The copper monoxide is expressed by (OCu2)x+(Cu1-2)y, where x and y satisfy inequalities 0.05-1 and 0.01-0.9 respectively. The tin monoxide is expressed by (OSn)z+(Sn1-2)w, where z and w satisfy inequalities 0.05-1 and 0.01-0.9 respectively. The copper tin oxide is expressed by (O-Cu-Sn)a+(Cu( alpha )-Sn( beta ))b, where alpha and beta satisfy inequalities 0-2 and 0-2 respectively, and a and b satisfy inequalities 0.05-1 and 0.01-0.9 respectively. The nickel tin oxide is expressed by (O-Ni)a-(Ni( alpha )-Sn( beta ))b, where alpha and beta satisfy inequalities 0-2 and 0-2 respectively, and a and b satisfy inequalities 0.05-1 and 0.01-0.9 respectively. The device further comprises a protective layer (14) disposed on the p-type oxide layer, an insulating layer disposed on or under the p-type oxide layer, a matching layer (12) interposed between the insulating layer and the p-type oxide layer, a gate electrode disposed on a substrate (11), a gate insulating layer disposed on the gate electrode, and source and drain electrodes configured to contact both ends of the channel layer, and an n-type semiconductor layer disposed on the substrate. The channel layer has a thickness of 0.5-100000 nm. The matching layer is interposed between the gate insulating layer and the channel layer and between the n-type semiconductor layer and the p-type semiconductor layer. The p-type semiconductor layer has a thickness of 5-100000 nm, and is used as a blocking layer configured to block electrons or holes, when the p-type oxide layer has an electrical conductivity of less than or equal to 10-6 S/cm. An INDEPENDENT CLAIM is included for a method of manufacturing a semiconductor device.    DESCRIPTION OF DRAWING(S) - The diagram shows a schematic cross-sectional view of a semiconductor device.    Semiconductor device (10)    Substrate (11)    Matching layer (12)    P-type oxide layer (13)    Protective layer. (14)