NOVELTY - The package has a passivation layer (104) e.g. glass substrate, located overlying an upper surface (100a) of a substrate (100) i.e. silicon wafer. A set of conducting pad structures (102) is formed overlying the upper surface of the substrate, so that portions of upper surfaces of the pad structures are exposed. A set of openings (112) extends from the upper surface toward a lower surface of the substrate. A set of movable bulks (114) is located between the openings, and is connected with the substrate. A set of conducting wires (110) connects the bulks and the corresponding pad structures.    USE - Chip package i.e. micro electro mechanical system (MEMS) chip package. Can also be used for an active or passive device, electronic component with digital or analog circuit, image sensor device, LED, solar cell, radiofrequency circuit, accelerator, gyroscope, pressure sensor or ink printer head.    ADVANTAGE - The movable bulks connect with the substrate only through the periphery portions, so that the movable bulks are easily prevented from bending or moving in response to application of external force to the chip package, thus increasing the sensing sensitivity of the package. The portion of the conducting pad structure is partially exposed, thus easily connecting the conducting pad structure with another conducting structure, thus facilitating integration with other electronic devices. The passivation layer covers a portion of the conducting pad structure, so that the upper surface of the conducting pad does not directly contact with any insulating material. The package includes an etch stop layer formed overlying the substrate such that the conducting pad structure is protected during forming the movable bulks, thus preventing the conducting pad from being damaged due to the etching process. The substrate is formed by a wafer-level package process, thus reducing fabrication cost and fabrication time of the substrate.    DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for forming a chip package.    DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view showing the steps for forming a chip package.    Substrate (100)    Upper surface of substrate (100a)    Conducting pad structures (102)    Passivation layer (104)    Conducting wires (110)    Openings (112)    Movable bulks (114)    Package layer (116)    Cavity (120)    Trench (122)    Conducting structure (124)