NOVELTY - The method involves forming an electrically conductive layer (132) over a semiconductor die (124) and an encapsulant (156). Another die (146) is placed over the conductive layer. Another encapsulant (140) is deposited around the latter die, while exposing a surface of the latter die including a contact pad (132). Another conductive layer (144) is formed over the latter die and the latter encapsulant electrically connected to the contact pad. A set of conductive vias (182) is formed through the conductive layers and through the encapsulants electrically connected to the conductive layers.    USE - Method for making an integrated semiconductor device. Uses include but are not limited to a microcontroller, microprocessor, charged-coupled device (CCD), solar cell and a digital micro-mirror device (DMD) for performing signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity and creating visual projections for TV displays in an entertainment field, communication field, power conversion field, networks, computers, consumer products, military applications, aviation applications, automotive applications, industrial controllers and office equipments.    ADVANTAGE - The method enables electronic devices to be manufactured using cheaper components and a streamlined manufacturing process, thus reducing failing of the devices, reducing expense for manufacture and reducing cost for consumers. The method enables the encapsulant to be deposited over a semiconductor package for environmental protection, thus preventing moisture and particles from entering the package and contaminating the semiconductor die or bond wires. The method enables providing a short electrical conduction path from active devices on the semiconductor die to conduction tracks, thus reducing signal propagation distance and lower capacitance and improving circuit performance.    DETAILED DESCRIPTION - The encapsulant is non-conductive molding compound. The conductive layers are redistribution layers (RDLs) or under bump metallization (UBM) layers. The surface is an active surface (130) or back surface (128). An INDEPENDENT CLAIM is also included for a semiconductor device.    DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a build-up interconnect structure formed over an embedded wafer level ball grid array (eWLB) package.    Semiconductor dies (124, 146, 166)    Back surfaces (128, 148, 168)    Active surfaces (130, 150, 170)    Electrically conductive layers (132, 144, 160, 172, 180, 186, 190, 208)    Encapsulants (140, 156, 176)    Conductive vias (182)