NOVELTY - The method comprises cleaning a silicon surface and removing a pre-existing native oxide layer, performing a low temperature oxide growth process to form an ultra-thin silicon oxide layer on the silicon surface, and performing a low temperature depositing process to deposit a doped, passivating dielectric layer on the ultra-thin silicon oxide layer. The ultra-thin silicon oxide layer has a thickness of less than 10 Angstrom . The low temperature depositing process and the low temperature oxide growth process are performed at temperatures below 500 degrees C.    USE - The method is useful for passivating a crystalline silicon surface that is useful in a structure of a semiconductor device such as a photovoltaic cell, a MOSFET device and a flash memory device (all claimed).    ADVANTAGE - The method allows passivation of the crystalline silicon surface with high quality and desired thickness thus economically forming the semiconductor device with high performance and density and lightweight and the solar cell with increased conversion efficiency.    DETAILED DESCRIPTION - The method comprises cleaning a silicon surface and removing a pre-existing native oxide layer, performing a low temperature oxide growth process to form an ultra-thin silicon oxide layer on the silicon surface, and performing a low temperature depositing process to deposit a doped, passivating dielectric layer on the ultra-thin silicon oxide layer. The ultra-thin silicon oxide layer has a thickness of less than 10 Angstrom . The low temperature depositing process and the low temperature oxide growth process are performed at temperatures below 500 degrees C. The low temperature oxide growth process is performed under ambient conditions such that the ultra-thin silicon oxide layer is a native oxide layer. The native oxide layer is formed over a time duration of greater than 150000 minutes. The method further comprises controlling humidity during the formation of the native oxide layer, depositing additional dielectric layers on the passivating dielectric layer, depositing a layer of a first doped material over a first region of the passivating dielectric layer, depositing a layer of a second doped material over a second region of the passivating dielectric layer, performing a suitable firing process in order to form a p-type hetero-/homo-junction with the crystalline silicon surface over the first region and an n-type hetero-/homo-junction with the crystalline silicon surface over the second region, and forming suitable electrical contacts at the first region and the second region. The low temperature oxide growth process is performed in an oxidizing environment and in the presence of ozone and performed by chemically oxidizing the silicon surface using a chemical oxidizing agent. The passivating dielectric layer is formed by a plasma enhanced chemical deposition (PECVD) process . The low temperature oxide growth process includes providing oxygen ions from catalytic dissociation of oxygen or hot-wire dissociation of oxygen. The plasma enhanced chemical deposition process is performed at temperatures of greater than 800 degrees C, and is based on hydrogen-containing precursor gases. The passivating dielectric layer is a semiconductor having dielectric properties, and has a thickness of 10-100 nm. The first region and the second region are spaced to form a semiconductor device. The first doped material and/or the second doped material is deposited by ink jet printing or silk screen printing.    DESCRIPTION OF DRAWING(S) - The figure shows a schematic view of a thin-film, flexible, solar cell structure.    Substrate (200)    N-doped hydrogenated amorphous silicon and metal contact electrode (210)    P-doped hydrogenated amorphous silicon and metal contact electrode. (220)