NOVELTY - Manufacturing (M1) multi-junction photovoltaic device comprises: providing silicon based solar cell from many solar cells, where silicon based solar cell has silicon substrate, first active cell and contact pattern; transferring silicon based solar cell to an additional sequence of process operations for second active region; forming a tunnel junction; forming the second active cell; forming contact layer; providing the multi-junction photovoltaic device to the silicon based solar module process; and outputting module including multi-junction photovoltaic device.    USE - The method is useful for manufacturing multi-junction photovoltaic device.    ADVANTAGE - The method provides photovoltaic devices that: allow uniform and consistent fabrication leading to improved yields and lower costs; exhibit increased efficiency; have greater design flexibility; have semiconductor layers with reduced thickness, thus reducing manufacturing costs; and reduce gallium/silicon relates shunts and other imperfections, thus avoiding short circuits. The method: exhibits high deposition rates and minimal changes to bottom cell emitter profile, and provides best tradeoff between absorption and low resistance; and employs growth process that occurs at low temperatures and short times to minimize diffusion of elements from the epitaxy into the silicon, thus providing controllable and repeatable profile.    DETAILED DESCRIPTION - Manufacturing (M1) a multi-junction photovoltaic device, comprises: providing a silicon based solar cell from many solar cells, where each solar cell forms a different manufacturing process, and the silicon based solar cell has a silicon substrate, a first active cell provided on the substrate, and a contact pattern to be provided, and is compatible for a silicon based module process, functional and compatible for the silicon based module process, free from any overlying contact metallization, and provided in wafer form; transferring the silicon based solar cell to an additional sequence of process operations for a second active region; forming a tunnel junction provided on the first active cell; forming the second active cell provided on the tunnel junction, where the tunnel junction includes a first semiconductor layer and a second semiconductor layer, and one of the first and second semiconductor layers includes at least aluminum or gallium; forming a contact layer overlying the second active region using the multi-junction contact pattern compatible with the silicon based solar module process; providing the multi-junction photovoltaic device to the silicon based solar module process; and outputting a module including the multi-junction photovoltaic device using the contact pattern. An INDEPENDENT CLAIM is also included for fabricating (M2) a multi-junction monolithically integrated photovoltaic device using a silicon-cell and module production compatible process, comprising: providing a silicon substrate, the silicon substrate having a surface region; providing a first active cell on the silicon substrate where the first active cell includes a base; subjecting the first active cell region to thermal process to form a buried emitter region in the first active region and cause formation of first active cell comprising a first surface region; cleaning the first surface region to be substantially free from organic or metallic contaminants; forming a termination layer overlying the first surface region, where the termination layer has a thickness of a gallium and phosphide bearing epitaxially formed material provided using at least metal organic chemical vapor deposition, hydride vapor phase epitaxy or vapor phase epitaxy process at a first temperature range and the thickness of the gallium and phosphide bearing epitaxial material comprising a region having a threading dislocation density of 1x 105 to 1x 107 cm-3; forming a tunnel junction region overlying the buried emitter region; forming a back surface field region overlying the tunnel junction region; and forming a second active cell using a second temperature range overlying the back surface field region, where the second active cell includes a base and an emitter, and is formed from at least one III-V semiconductor layers and has a threading dislocation density of 1x 105 to 1x 107 cm-3 and the first and second active cell regions have a cell level efficiency of 25-37%.