NOVELTY - Metalization and interconnection of a back-contacted back-junction silicon solar wafer (1) (where the solar wafer has e.g. (a) a layered stratified doped structure at least containing back-side emitter layer and base layer below the emitter layer that is formed into a multiplicity of alternating emitter- and base regions on back-side, and (b) a front side texturing and surface passivation), comprises: e.g. depositing continuous amorphous silicon layer onto back-side of wafer covering the emitter- and base regions; and depositing first insulation layer covering the silicon layer.    USE - The method is useful for metalization and interconnection of a back-contacted back-junction silicon solar wafer, which is useful in a back-contacted back-junction silicon solar cell or solar module (all claimed).    ADVANTAGE - The method: provides the back-contacted back-junction silicon solar wafer, which provides solar cells exhibiting increased efficiency and conversion efficiency; minimizes resistive losses and charge carrier recombination; alleviates the problems of bending and eventual fracturing of the brittle silicon wafers; and eliminates the step of patterning the second insulation layer, hence it is simple, and saves cost and energy.    DETAILED DESCRIPTION - Metalization and interconnection of a back-contacted back-junction silicon solar wafer (1)(where the solar wafer has (a) a layered stratified doped structure at least containing a back-side emitter layer and a base layer below the emitter layer that is formed into a multiplicity of alternating emitter- and base regions on the back-side by locally removing rectangular equidistant sections of the emitter layer from one side to the opposite side of the wafer to expose the underlying base layer, (b) a front side texturing and surface passivation, and (c) optionally an anti-reflective coating), comprises: depositing a continuous amorphous silicon layer onto the back-side of the wafer covering the multiplicity of alternating emitter- and base regions; depositing a first insulation layer covering the amorphous silicon layer except for one rectilinear opening running in parallel with and located more or less directly above the center-axis of each of the linear emitter- and base regions in the interdigitated multiplicity defining an electric contact access area above each of the linear emitter- and base regions of the interdigitated multiplicity of the wafer; forming the metalization of the wafer by one of depositing a continuous metal layer or stack of metal layers covering the first insulation layer that includes contact access areas, and then pattering the metal layer or stack of metal layers into one finger conductor (14) for each emitter- and base regions of the interdigitated multiplicity of the wafer, or depositing a patterned metal layer or stack of metal layers covering the first insulation layer that includes the contact access areas defining one finger conductor for each emitter- and base regions of the interdigitated multiplicity of the wafer; and depositing a second insulation layer onto the finger conductors with a set of access openings at positions where electric contact with the underlying finger conductor is intended, and forming a via contact in each access opening in the second insulation layer in electric contact with the finger conductor lying below the access opening. The electric contact with the underlying emitter- and base regions of the wafer is obtained by: employing aluminum or aluminum-silicon alloy as the first layer of the metalization being in contact with the amorphous silicon in the access openings in the first insulation layer; and heating the wafer up to at least 200 degrees C to obtain a crystallization of the amorphous silicon in between the metalization and silicon wafer in the access openings. INDEPENDENT CLAIMS are also included for:    (1) a back-contacted back-junction silicon solar cell, comprising: a crystalline silicon wafer having the layered stratified doped structure, the front side texturing and surface passivation, and optionally the anti-reflective coating; the back-side surface passivation in the form of a continuous amorphous silicon layer deposited directly onto and covering the multiplicity of alternating emitter- and base regions; the first insulation layer deposited onto and covering the continuous amorphous silicon layer except for one rectilinear opening running in parallel with and located more or less directly above the center-axis of each of the linear emitter- and base regions in the interdigitated multiplicity; the continuous metal layer or stack of metal layers deposited onto the first insulation layer that includes the contact access areas and is patterned into one finger conductor for each emitter- and base regions of the interdigitated multiplicity of the wafer; and the second insulation layer deposited onto the finger conductors having a set of access openings containing a via contact in electric contact with the underlying finger conductor, where the first layer of the metal layer or stack or layers being in contact with the amorphous silicon in the access openings in the first insulation layer is either aluminum or aluminum-silicon alloy, and the amorphous silicon in between the metal layer or stack of layers and the silicon wafer is crystallized; and    (2) a back-contacted back-junction silicon solar module, comprising: a multiplicity of k x l solar cells (where k and l are greater than or equal to 1) laminated to a module front substrate in rectangular a tessellated-resembling pattern of k rows and l columns with their front- side facing the module front substrate; a set of ribbons (20, 21) on top of the second insulation layer in electric contact with an intended selection of via contacts in the second insulation layer; and a back-side cover substrate laminated onto the back-side of the module front, so that the multiplicity of solar cells including the deposited layers are sandwiched and encapsulated by the lamination adhesive between the module front and back substrate.    DESCRIPTION OF DRAWING(S) - The figure shows a schematic view of a second insulation layer and ribbon geometry.    Wafer (1)    Finger conductors (14)    Ribbons (20, 21)