NOVELTY - The method involves providing a semiconductor die (122), and forming a conductive via in the semiconductor die. A trench is formed along length of a peripheral region of the semiconductor die. A conductive layer (138) is deposited in the trench and the via, where another conductive layer (140) is formed over an active surface (124) of the semiconductor die. An insulating layer (136) is formed in the trench and the via. The trench is filled with the conductive layers. The semiconductor dies coupled through the via are stacked, where the trench includes an area larger than an area of the via.    USE - Method for making a discrete semiconductor device for an electronic product. Uses include but are not limited to microcontrollers, microprocessors, graphics card, network interface card, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs) for entertainment, communications, power conversion, networks, computers and consumer product fields, military applications, aviation, automotive, industrial controllers, and office equipment.    ADVANTAGE - The method enables producing smaller semiconductor devices in an efficient manner such that the device consumes less power and obtains higher performance, thus manufacturing the electronic devices using a streamlined manufacturing process in a cost-effective manner. The method allows efficiently and cost effectively forming conductive vias to electrically interconnect stacked semiconductor die. The method allows simultaneous formation of the conductive layers in the vias so that the manufacturing process is simplified. The method allows forming the trench with larger area and lower aspect ratio, so that the formation of the conductive layer is accelerated to fill the vias, thus reducing void formation, and minimizing defects, and hence increasing reliability of the semiconductor device, and obtaining better production yield and compact package size.    DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a semiconductor device.    DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a vertically stacked semiconductor die electrically connected with conductive vias and a redistribution layer.    Semiconductor die (122)    Active surface of semiconductor die (124)    Contact pad (126)    Insulating layer (136)    Conductive layers (138, 140)