NOVELTY - The method involves providing a semiconductor substrate (202) including a patterned mask layer (204) that is formed on the substrate corresponding to a set of shallow trench isolation structures to be etched. The substrate is etched through the patterned mask layer by using plasma formed from process gas to form shallow trench isolation structure recesses (214) on the substrate. The plasma is pulsed for a portion of etching the substrate by pulsing biasing power and source power to control depth or width of the shallow trench isolation structure recesses.    USE - Method for fabricating shallow trench isolation structures i.e. high aspect ratio shallow trench isolation structures, in a semiconductor substrate for an advanced or very small node device e.g. flash memory device and DRAM device. Uses include but are not limited to a semiconductor wafer, a doped or un-doped silicon substrate, a III-V compound substrate, a silicon germanium substrate, an epi-substrate, a silicon-on-insulator substrate and a display substrate e.g. LCD substrate, plasma display substrate, electro luminescence lamp display substrate, LED substrate, solar cell array substrate and solar panel substrate.    ADVANTAGE - The method enables controlling cell microloading between adjacent cells or isolated/dense microloading between areas of isolated or dense features during shallow trench isolation fabrication processes to meet different requirements for different customer applications, thus providing improved and flexible control over etch depth microloading among individual features, features and peripheral areas, regions of dense features and regions of isolated features, and hence fabricating the shallow trench isolation structures with high aspect ratio in an efficient manner.    DETAILED DESCRIPTION - The process gas is selected from a group consisting of fluorine-containing gas, fluorocarbon, hydrofluorocarbon-containing gas and inert gas e.g. nitrogen, helium and argon. The substrate comprises a set of intervening layers (212) formed of polysilicon e.g. polycrystalline silicon and tunnel oxide.    DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a substrate in different stages for fabricating shallow trench isolation structures.    Semiconductor substrate (202)    Patterned mask layer (204)    High feature density area (208)    Low feature density area (210)    Intervening layers (212)    Shallow trench isolation structure recesses (214)